IEEE VLSI PROJECT'S


IEEE 2018 Vlsi Titles

SNo Project Title Domain Year
VLSI1 A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS Low Power VERILOG/VHDL/2018
VLSI2 A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications Low Power VERILOG/VHDL/2018
VLSI3 A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing Low Power VERILOG/VHDL/2018
VLSI4 A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop Low Power VERILOG/VHDL/2018
VLSI5 A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number Low Power VERILOG/VHDL/2018
VLSI6 A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata Low Power VERILOG/VHDL/2018
VLSI7 A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications Low Power VERILOG/VHDL/2018
VLSI8 Approximate Sum-of-Products Designs Based on Distributed Arithmetic Low Power VERILOG/VHDL/2018
VLSI9 Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation Low Power VERILOG/VHDL/2018
VLSI10 Design of an Area-Efficient Million-Bit Integer Multiplier Using Double Modulus NTT Low Power VERILOG/VHDL/2018
VLSI11 Design of Temperature-Aware Low-Voltage 8T SRAM in SOI Technology for High-Temperature Operation (25 °C–300 °C) Low Power VERILOG/VHDL/2018
VLSI12 Improving Error Correction Codes for Multiplier Cel Upsets in Space Applications Low Power VERILOG/VHDL/2018
VLSI13 Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates Low Power VERILOG/VHDL/2018
VLSI14 Securing the PRESENT Block Cipher Against Combined Side-Channel Analysis and Fault Attacks Low Power VERILOG/VHDL/2018
VLSI15 SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability Low Power VERILOG/VHDL/2018
VLSI16 The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection Low Power VERILOG/VHDL/2018
VLSI17 ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures Low Power VERILOG/VHDL/2018
VLSI18 Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add Low Power VERILOG/VHDL/2018
VLSI19 A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation High Speed Data Transmission VERILOG/VHDL/2018
VLSI20 A Fast-Locking, Low-Jitter Pulse width Control Loop for High-Speed ADC High Speed Data Transmission VERILOG/VHDL/2018
VLSI21 A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata High Speed Data Transmission VERILOG/VHDL/2018
VLSI22 A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution High Speed Data Transmission VERILOG/VHDL/2018
VLSI23 A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition High Speed Data Transmission VERILOG/VHDL/2018
VLSI24 Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities High Speed Data Transmission VERILOG/VHDL/2018
VLSI25 Approximate Error Detection With Stochastic Checkers High Speed Data Transmission VERILOG/VHDL/2018
VLSI26 Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers High Speed Data Transmission VERILOG/VHDL/2018
VLSI27 Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding High Speed Data Transmission VERILOG/VHDL/2018
VLSI28 Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications High Speed Data Transmission VERILOG/VHDL/2018
VLSI29 Efficient FPGA Mapping of Pipeline SDF FFT Cores High Speed Data Transmission VERILOG/VHDL/2018
VLSI30 Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction High Speed Data Transmission VERILOG/VHDL/2018
VLSI31 Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design High Speed Data Transmission VERILOG/VHDL/2018
VLSI32 Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption High Speed Data Transmission VERILOG/VHDL/2018
VLSI33 The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection High Speed Data Transmission VERILOG/VHDL/2018
VLSI34 Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add High Speed Data Transmission VERILOG/VHDL/2018
VLSI35 A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications Area Efficient VERILOG/VHDL/2018
VLSI36 A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme Area Efficient VERILOG/VHDL/2018
VLSI37 A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing Area Efficient VERILOG/VHDL/2018
VLSI38 A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n − 1, 2n + 1, 22n + 1, 22n+p} Area Efficient VERILOG/VHDL/2018
VLSI39 A Simple Yet Efficient Accuracy Configurable Adder Design Area Efficient VERILOG/VHDL/2018
VLSI40 An Efficient Fault-Tolerance Design for Integer Parallel Matrix–Vector Multiplications Area Efficient VERILOG/VHDL/2018
VLSI41 Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders Area Efficient VERILOG/VHDL/2018
VLSI42 Approximate Error Detection With Stochastic Checkers Area Efficient VERILOG/VHDL/2018
VLSI43 Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers Area Efficient VERILOG/VHDL/2018
VLSI44 Basic-Set Trellis Min–Max Decoder Architecture for Non binary LDPC Codes With High-Order Galois Fields Area Efficient VERILOG/VHDL/2018
VLSI45 Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction Area Efficient VERILOG/VHDL/2018
VLSI46 Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method Area Efficient VERILOG/VHDL/2018
VLSI47 Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy Area Efficient VERILOG/VHDL/2018
VLSI48 Low-Complexity Methodology for Complex Square-Root Computation Area Efficient VERILOG/VHDL/2018
VLSI49 Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits Area Efficient VERILOG/VHDL/2018
VLSI50 Securing the PRESENT Block Cipher Against Combined Side-Channel Analysis and Fault Attacks Area Efficient VERILOG/VHDL/2018
VLSI51 ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures Area Efficient VERILOG/VHDL/2018
VLSI52 VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems Area Efficient VERILOG/VHDL/2018
VLSI53 VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems Audio, Image And Video Processing VERILOG/VHDL/2018
VLSI54 An Energy-Efficient Programmable Many core Accelerator for Personalized Biomedical Applications Audio, Image And Video Processing VERILOG/VHDL/2018
VLSI55 A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications Tanner(Nm) / Hspice(Nm) / Dsch3 - Microwind(Um) VERILOG/VHDL/2018
VLSI56 A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop Tanner(Nm) / Hspice(Nm) / Dsch3 - Microwind(Um) VERILOG/VHDL/2018
VLSI58 Design of Temperature-Aware Low-Voltage 8T SRAM in SOI Technology for High-Temperature Operation (25 °C–300 °C) Tanner(Nm) / Hspice(Nm) / Dsch3 - Microwind(Um) VERILOG/VHDL/2018
VLSI59 A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications Tanner(Nm) / Hspice(Nm) / Dsch3 - Microwind(Um) VERILOG/VHDL/2018
VLSI60 Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design Tanner(Nm) / Hspice(Nm) / Dsch3 - Microwind(Um) VERILOG/VHDL/2018
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