IEEE VLSI PROJECT'S


IEEE 2021 Vlsi Titles

SNo Project Title Domain Year
VLSI1 ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential Equation Solver Low power VHDL/2021
VLSI2 A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator Low power VHDL/2021
VLSI3 FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction Low power VHDL/2021
VLSI4 An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power Low power VHDL/2021
VLSI5 FPGA-Based High-Definition SPWM Generation With Harmonic Mitigation Property for Voltage Source Inverter Applications Low power VHDL/2021
VLSI6 Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS Low power VHDL/2021
VLSI7 Review of Analog-Assisted-Digital and Digital-Assisted-Analog Low Dropout Regulators Low power VHDL/2021
VLSI8 A 65nm 0.6–1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter With Direct Output Feedback Low power VHDL/2021
VLSI9 An Ultra-Low Quiescent Current Resistor-Less Power on Reset Circuit Low power VHDL/2021
VLSI10 A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL Low power VHDL/2021
VLSI11 Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology Low power VHDL/2021
VLSI12 EMI Effect in Voltage-to-Time Converters Low power VHDL/2021
VLSI13 Correlation-Based Background Calibration of Bit Weight in SAR ADCs Using DAS Algorithm Low power VHDL/2021
VLSI14 Power Efficiency Model for MIMO Transmitters Including Memory Polynomial Digital Predistortion Low power VHDL/2021
VLSI15 BCD Adder Designs Based on Three-Input XOR and Majority Gates Low power VHDL/2021
VLSI16 A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback Low power VHDL/2021
VLSI17 Coupled Variable Input-LCG and Clock Divider based Large Period Pseudo-Random Bit Generator on FPGA Low area and Delay efficient VHDL/2021
VLSI18 Automatic heart disease class detection using convolutional neural network architecture‐based various optimizers‐networks Low area and Delay efficient VHDL/2021
VLSI19 The DFA/DFT-based hacking techniques and countermeasures: Case study of the 32-bit AES encryption crypto-core Low area and Delay efficient VHDL/2021
VLSI20 Power Efficiency Model for MIMO Transmitters Including Memory Polynomial Digital Predistortion Low area and Delay efficient VHDL/2021
VLSI21 A novel FPGA‐Based Bi input‐reduced order extended Kalman filter for speed‐sensorless direct torque control of induction motor with constant switching frequency controller Low area and Delay efficient VHDL/2021
VLSI22 Multi-precision binary multiplier architecture for multi-precision floating-point multiplication Low area and Delay efficient VHDL/2021
VLSI23 Design and Calibration Techniques for a Multichannel FPGA-Based Time-to-Digital Converter in an Object Positioning System Low area and Delay efficient VHDL/2021
VLSI24 Spatial Information Based OSort for Real-Time Spike Sorting Using FPGA Low area and Delay efficient VHDL/2021
VLSI25 Full-Duplexing with SDR Devices: Algorithms, FPGA Implementation and Real-Time Results Low area and Delay efficient VHDL/2021
VLSI26 High-Throughput FPGA Implementation of Matrix Inversion for Control Systems Low area and Delay efficient VHDL/2021
VLSI27 Design of Ultra-Low Power Consumption Approximate 4–2 Compressors Based on the Compensation Characteristic Low area and Delay efficient VHDL/2021
VLSI28 Improvement of Accuracy of Fixed-Width Booth Multipliers Using Data Scaling Technology Low area and Delay efficient VHDL/2021
VLSI29 Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures Low area and Delay efficient VHDL/2021
VLSI30 An Efficient NB-LDPC Decoder Architecture for Space Telecommand Links Low area and Delay efficient VHDL/2021
VLSI31 Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography High Speed Transmission VHDL/2021
VLSI32 Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization High Speed Transmission VHDL/2021
VLSI33 Two‐dimensional DFT with sliding and hopping windows for edge map generation of road images High Speed Transmission VHDL/2021
VLSI34 The implementation of the clustered-OFDM-based transceiver on an FPGA device: A comprehensive comparison High Speed Transmission VHDL/2021
VLSI35 Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors High Speed Transmission VHDL/2021
VLSI36 FPGA-based implementation of floating point processing element for the design of efficient FIR filters High Speed Transmission VHDL/2021
VLSI37 Fast OMP algorithm and its FPGA implementation for compressed sensing-based sparse signal acquisition systems High Speed Transmission VHDL/2021
VLSI38 Low-Cost and Programmable CRC Implementation Based on FPGA High Speed Transmission VHDL/2021
VLSI39 A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance High Speed Transmission VHDL/2021
VLSI40 A Graph-Temporal Fused Dual-Input Convolutional Neural Network for Detecting Sleep Stages from EEG Signals High Speed Transmission VHDL/2021
VLSI41 A Memory-Reduced Frequency Estimator for the Measurement of Sinusoidal Signal High Speed Transmission VHDL/2021
VLSI42 A Type-I PLL With Foreground Loop Bandwidth Calibration High Speed Transmission VHDL/2021
VLSI43 A Fractional Order Notch Filter to Compensate the Attenuation-Loss Due to Change in Order of the Circuit High Speed Transmission VHDL/2021
VLSI44 Design and implementation of image kernels using reversible logic gates AUDIO / IMAGE & VIDEO Processing VHDL/2021
VLSI45 Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption AUDIO / IMAGE & VIDEO Processing VHDL/2021
VLSI46 A 3.3 Gbps CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA AUDIO / IMAGE & VIDEO Processing VHDL/2021
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