VLSI IEEE PROJECT'S


1. Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits

2. A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational

3. Sequential Circuits

4. Ultralow-Energy Variation-Aware Design: Adder Architecture Study

5. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

7. High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols

9. Median Filter Architecture by Accumulative Parallel Counters

10. A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM

11. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

12. High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding

13. A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices

14. Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

15. Further Desensitized FIR Halfband Filters

16. Implementation of Arithmetic Operations with Time-free Spiking Neural P Systems

17. A Clock and Data Recovery Circuit With Programmable Multi-Level Phase Detector Characteristics and a Built-in Jitter Monitor

18. Early Skip Mode Decision for HEVC Encoder With Emphasis on Coding Quality

19. Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters

20. Energy Consumption of VLSI Decoders

21. Timing Error Tolerance in Small Core Designs for SoC Applications

22. Design and Analysis of Inexact Floating-Point Adders

23. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

24. Low-Cost High-Performance VLSI Architecture for Montgomery ModularMultiplication

25. Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA

26. A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory

27. Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception

28. Synthesis of Genetic Clock with Combinational Biologic Circuits

29. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number Systems

30. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability

31. Novel Block-Formulation and Area-Delay-Ef?cient Recon?gurable Interpolation Filter Architecture for Multi-Standard SDR Applications

32. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

33. Low-Power and Area-Efficient Shift Register Using Pulsed Latches

34. Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design

35. Recursive Approach to the Design of a Parallel Self-Timed Adder

36. Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq

37. An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

38. A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

39. A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator

40. A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

41. A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes

42. Design of Efficient Content Addressable Memories in High-Performance FinFET Technology

43. A New Efficiency-Improvement Low-Ripple Charge-Pump Boost Converter Using Adaptive Slope Generator With Hysteresis Voltage Comparison Techniques

44. Obfuscating DSP Circuits via High-Level Transformations

45. Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms

46. Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging

47. Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

48. All Digital Energy Sensing for Minimum Energy Tracking

49. Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications

50. Algorithm and Architecture Design of the H.265/HEVC Intra Encoder

51. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding

52. A Novel Photosensitive Tunneling Transistor for Near-Infrared Sensing Applications: Design, Modeling, and Simulation

53. High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

54. A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

55. Graph-Based Transistor Network Generation Method for Supergate Design

56. A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications

57. Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

58. A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders

59. Comparative Performance Analysis of the Dielectrically Modulated FullGate and Short-Gate Tunnel FET-Based Biosensors

60. VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm

61. Fine-Grained Access Management in Reconfigurable Scan Networks

62. A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

63. Partially Parallel Encoder Architecture for Long Polar Codes

64. One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes

65. A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications

66. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

67. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications

68. A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register

69. A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply

70. A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

71. Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

72. Design and Low-Complexity Implementation of Matrix-Vector Multiplier for Iterative Methods in Communication Systems

73. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

74. The Diffusion Network in Analog VLSI Exploiting Noise-Induced Stochastic Dynamics to Regenerate Various Continuous Paths

75. Nonsmooth Optimization Method for VLSI Global Placement

76. Low-Power VLSI Architectures for DCT/DWT: Precision vs Approximation for HD Video, Biomedical, and Smart Antenna Applications

77. VLSI Design for SVM-Based Speaker Verification System

78. An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation

79. Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach

80. A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

81. Ultra-High-Throughput VLSI Architecture of H.265 HEVC CABAC Encoder for UHDTV Applications

82. Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI

83. A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification

84. Reconfiguration-Based VLSI Design for Security

85. Depth-Reliability-Based Stereo-Matching Algorithm and Its VLSI Architecture Design

86. Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs

87. A Bio-Realistic Analog CMOS Cochlea Filter With High Tunability and Ultra-Steep Roll-Off

88. Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection

89. A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF (2^{m})

90. Multilayer Obstacle-Avoiding X-Architecture Steiner Minimal Tree Construction Based on Particle Swarm Optimization

91. Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

92. ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip

93. A Novel Hardware Architecture of the Lucas-Kanade Optical Flow for Reduced Frame Memory Access

94. Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems

95. Detailed Routing Algorithms for Advanced Technology Nodes

96. A Low-Complexity Embedded Compression Codec Design With Rate Control for High-Definition Video

97. Fast Motion Estimation Algorithm And Design For Real Time QFHD High Efficiency Video Coding

98. Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

99. A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures

100. A Power-Efficient Adaptive Fuzzy Resolution Control System for Wireless Body Sensor Networks

101. Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing

102. Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set

103. Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline

104. New Analytic Model of Coupling and Substrate Capacitance in Nanometer Technologies

105. A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning

106. Area-Efficient Fixed-Width Squarer with Dynamic Error-Compensation Circuit

107. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

108. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

109. An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Non-binary LDPC Codes

110. Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay

111. Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

112. An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

113. High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations

114. A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Pre-scaler

115. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability

116. Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 ? 1, 2n ? 1, 2n}

117. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

118. Variable Latency Speculative Han-Carlson Adder

119. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

120. High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic

121. Area-Delay-Power Efficient Carry-Select Adder

122. Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm

123. A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications

124. Low-Power and Area-Efficient Shift Register Using Pulsed Latches

125. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

126. Data encoding techniques for reducing energy Consumption in network-on-chip

127. Wear out Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm

128. Low-Power Programmable PRPG With Test Compression Capabilities

129. Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

130. Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications

131. Trade-Offs for Threshold Implementations Illustrated on AES

132. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

133. A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

134. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System

135. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications

136. Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT

137. Design and Analysis of Approximate Compressors for Multiplication

138. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

139. Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

140. Graph-Based Transistor Network Generation Method for Super gate Design

141. Recursive Approach to the Design of a Parallel Self-Timed Adder